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Registration for XJTAG Free Hands-on Practical Boundary Scan Webinars

Date and Time: 26th August (Wednesday) 2020, 2:30pm to 5.30pm IST-INDIA
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  The 2 to 3 hour sessions are designed to provide design, development, test, and production engineers with a practical hands-on introduction to JTAG boundary scan, using real hardware. You will have access to a full XJTAG development system to give you the experience of actively developing and running boundary scan tests.

The webinar will be run by an experienced engineer (all you need is a web browser). No prior knowledge of JTAG is required.

A recording of the webinar will be made available afterwards, as will further hardware access time should you wish to review the webinar content.

Introduction to JTAG - Concepts, Tools & Design for Test (DFT)


Learn the basics of boundary scan and how you can use it right across the product lifecycle to improve designs, reduce respins and enhance test coverage, fault diagnosis and production yields on complex BGA-populated circuits. The webinar outlines the following:

  
 
  • Overview of the IEEE 1149.x standards
  • How to communicate with the JTAG chain
  • Tools to interact with JTAG devices, such as FPGAs or Processors
  • Introduction to board testing using the JTAG chain
  • How to describe a circuit in order to enable JTAG testing
  • Fault finding abilities of a JTAG connection test
  • How to test non-JTAG elements of a board design using boundary scan

 
 
     
 
     
 
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